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- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2016
-
Mark
A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters
(
- Contribution to journal › Article
- 2015
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Mark
A Noise-Cancelling Receiver Front-End with Frequency Selective Input Matching
(
- Contribution to journal › Article
- 2014
-
Mark
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
(
- Contribution to journal › Article
-
Mark
A Filtering Delta Sigma ADC for LTE and Beyond
(
- Contribution to journal › Article
- 2013
-
Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
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Mark
An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
(
- Contribution to journal › Article
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Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
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Mark
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS
(
- Contribution to journal › Article
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Mark
A Push-Pull Class-C CMOS VCO
(
- Contribution to journal › Article