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- 2024
-
Mark
Efficient Wideband mmW Transceiver Front End for 5G Base Stations in 22-nm FD-SOI CMOS
(
- Contribution to journal › Article
- 2022
-
Mark
A 12-GHz Reconfigurable Multicore CMOS DCO, With a Time-Variant Analysis of the Impact of Reconfiguration Switches on Phase Noise
(
- Contribution to journal › Article
- 2021
-
Mark
A Type-II Phase-Tracking Receiver
(
- Contribution to journal › Article
- 2020
-
Mark
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
(
- Contribution to journal › Article
-
Mark
A 19.5-GHz 28-nm Class-C CMOS VCO, with a reasonably rigorous result on 1/f noise upconversion caused by short-channel effects
(
- Contribution to journal › Article
- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2016
-
Mark
A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters
(
- Contribution to journal › Article
- 2015
-
Mark
A Noise-Cancelling Receiver Front-End with Frequency Selective Input Matching
(
- Contribution to journal › Article
- 2014
-
Mark
A Power-Scalable DCO for Multi-Standard GSM/WCDMA Frequency Synthesizers
(
- Contribution to journal › Article
-
Mark
A Filtering Delta Sigma ADC for LTE and Beyond
(
- Contribution to journal › Article
- 2013
-
Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
-
Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
-
Mark
An 0.8-mm(2) 9.6-mW Iterative Decoder for Faster-Than-Nyquist and Orthogonal Signaling Multicarrier Systems in 65-nm CMOS
(
- Contribution to journal › Article
-
Mark
A Push-Pull Class-C CMOS VCO
(
- Contribution to journal › Article
-
Mark
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS
(
- Contribution to journal › Article
- 2012
-
Mark
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
(
- Contribution to journal › Debate/Note/Editorial
-
Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
- 2011
-
Mark
A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
(
- Contribution to journal › Article
-
Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
(
- Contribution to journal › Article
- 2009
-
Mark
Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback
(
- Contribution to journal › Article
- 2008
-
Mark
Sensitivity degradation in a tri-band GSM BiCMOS direct-conversion receiver caused by transient substrate heating
(
- Contribution to journal › Article
-
Mark
Comments on "Comments on "A General Theory of Phase Noise in Electrical Oscillators""
(
- Contribution to journal › Letter
-
Mark
Class-C Harmonic CMOS VCOs, With a General Result on Phase Noise
(
- Contribution to journal › Article
- 2007
-
Mark
An analysis of 1/f2 phase noise in bipolar colpitts oscillators (With a digression on bipolar differential-pair LC oscillators)
(
- Contribution to journal › Article
- 2006
-
Mark
Single-stage low-power quadrature RF receiver front-end: the LMV cell
(
- Contribution to journal › Article
-
Mark
More on the 1/f2 Phase Noise Performance of CMOS Differential-Pair LC-Tank Oscillators
(
- Contribution to journal › Article
-
Mark
On the amplitude and phase errors of quadrature LC-tank CMOS oscillators
(
- Contribution to journal › Article
- 2005
-
Mark
Highly integrated direct conversion receiver for GSM/GPRS/EDGE with on-chip 84-dB dynamic range continuous-time ΣΔ ADC
(
- Contribution to journal › Article
-
Mark
A study of phase noise in colpitts and LC-tank CMOS oscillators
(
- Contribution to journal › Article
-
Mark
Low-power voltage-controlled oscillators in 90-nm CMOS using high-quality thin-film postprocessed inductors
(
- Contribution to journal › Article
- 2004
-
Mark
A digitally controlled PLL for SoC applications
(
- Contribution to journal › Article
-
Mark
On the phase-noise and phase-error performances of multiphase LC CMOS VCOs
(
- Contribution to journal › Article
- 2003
-
Mark
A merged CMOS LNA and mixer for a WCDMA receiver
(
- Contribution to journal › Article
-
Mark
A 8-bit 100-MHz CMOS linear interpolation DAC
(
- Contribution to journal › Article
-
Mark
A 10-bit wide-band CMOS direct digital RF amplitude modulator
(
- Contribution to journal › Article
- 2002
-
Mark
Tail current noise suppression in RF CMOS VCOs
(
- Contribution to journal › Article
-
Mark
On the use of Nauta's transconductor in low-frequency CMOS g(m)-C bandpass filters
(
- Contribution to journal › Article
-
Mark
Analysis and design of a 1.8-GHz CMOS LC quadrature VCO
(
- Contribution to journal › Article
- 2001
-
Mark
A 2.2 GHz CMOS VCO with inductive degeneration noise suppression
2001) p.197-200(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A filtering technique to lower LC oscillator phase noise
(
- Contribution to journal › Article
- 2000
-
Mark
A low logic depth complex multiplier using distributed arithmetic
(
- Contribution to journal › Article
-
Mark
On the use of MOS varactors in RF VCOs
(
- Contribution to journal › Article
- 1998
-
Mark
A 160MHz bipolar wideband IF amplifier
(
- Contribution to journal › Article
-
Mark
A 100MHz CMOS wideband IF amplifier
(
- Contribution to journal › Article
-
Mark
Multihit multichannel time-to-digital converter with ±1% differential nonlinearity and near optimal time resolution
(
- Contribution to journal › Article
- 1997
-
Mark
New single clock CMOS latches and flipflops with improved speed and power savings
(
- Contribution to journal › Article
-
Mark
A Custom Digital Intermediate Frequency Filter for the American Mobile Telephone System
(
- Contribution to journal › Article
- 1996
-
Mark
A Monolithic Digital Clock-Generator for On-Chip Clocking of Custom DSP's
(
- Contribution to journal › Article
- 1994
-
Mark
A 3-level asynchronous protocol for a differential two-wire communication link
(
- Contribution to journal › Article
-
Mark
A 10-bit 5-MS/s successive approximation ADC cell used in a 70-MS/s ADC array in 1.2-um CMOS
(
- Contribution to journal › Article
- 1993
-
Mark
A 700-MHZ 24-bit pipelined accumulator in 1.2-um CMOS for application as a numerically controlled oscillator
(
- Contribution to journal › Article
- 1991
-
Mark
Double-edge-triggered D-flip-flop for high speed CMOS circuits
(
- Contribution to journal › Article
- 1989
-
Mark
High speed CMOS circuit technique
(
- Contribution to journal › Article
- 1987
-
Mark
A true single-phase-clock dynamic CMOS circuit technique
(
- Contribution to journal › Letter