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- 2013
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Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
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A Push-Pull Class-C CMOS VCO
(
- Contribution to journal › Article
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Mark
A 2.7-6.1 GHz CMOS local oscillator based on frequency multiplication by 3/2
(
- Contribution to journal › Article
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Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
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Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
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Mark
Introduction to the Special Issue on the 2012 IEEE International Solid-State Circuits Conference
(
- Contribution to journal › Debate/Note/Editorial
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Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
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Mark
Phase Noise Analysis of the Tuned-Input-Tuned-Output (TITO) Oscillator
(
- Contribution to journal › Article
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Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
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Mark
A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
Time-variant analysis and design of a power efficient ISM-band quadrature receiver
(
- Contribution to journal › Article
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Mark
A TX VCO for WCDMA/EDGE in 90 nm RF CMOS
(
- Contribution to journal › Article
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Mark
Single-ended low noise multiband LNA with programmable integrated matching and high isolation switches
2011) p.1-4(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A mixed mode design flow for multi GHz ADPLLs
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding