Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(2019) In IEEE Journal of the Electron Devices Society 7. p.70-75- Abstract
Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric... (More)
Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/μm, high on-current, and off-current below 1 nA/μm. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.
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- author
- Kilpi, Olli Pekka LU ; Svensson, Johannes LU ; Lind, Erik LU and Wernersson, Lars Erik LU
- organization
- publishing date
- 2019
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- Fabrication, heterostructure., InAs, InGaAs, Logic gates, MOSFET, nanowire, Resistance, Scattering, Semiconductor device modeling, Vertical
- in
- IEEE Journal of the Electron Devices Society
- volume
- 7
- pages
- 70 - 75
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85055884047
- ISSN
- 2168-6734
- DOI
- 10.1109/JEDS.2018.2878659
- language
- English
- LU publication?
- yes
- id
- dec0a29c-305a-4a9d-ab76-928b35c11574
- date added to LUP
- 2018-11-20 08:42:19
- date last changed
- 2023-09-22 11:49:26
@article{dec0a29c-305a-4a9d-ab76-928b35c11574, abstract = {{<p>Vertical InAs/InGaAs nanowire MOSFETs are fabricated in a gate-last fabrication process, which allows gate-lengths down to 25 nm and accurate gate-alignment. These devices demonstrate high performance with transconductance of 2.4 mS/&#x03BC;m, high on-current, and off-current below 1 nA/&#x03BC;m. An in-depth analysis of the heterostructure MOSFETs are obtained by systematically varying the gate-length and gate location. Further analysis is done by using virtual source modeling. The injection velocities and transistor metrics are correlated with a quasi-ballistic 1-D MOSFET model. Based on our analysis, the observed performance improvements are related to the optimized gate-length, high injection velocity due to asymmetric scattering, and low access resistance.</p>}}, author = {{Kilpi, Olli Pekka and Svensson, Johannes and Lind, Erik and Wernersson, Lars Erik}}, issn = {{2168-6734}}, keywords = {{Fabrication; heterostructure.; InAs; InGaAs; Logic gates; MOSFET; nanowire; Resistance; Scattering; Semiconductor device modeling; Vertical}}, language = {{eng}}, pages = {{70--75}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Journal of the Electron Devices Society}}, title = {{Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs}}, url = {{http://dx.doi.org/10.1109/JEDS.2018.2878659}}, doi = {{10.1109/JEDS.2018.2878659}}, volume = {{7}}, year = {{2019}}, }