Henrik Sjöland
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- 2013
-
Mark
A 3 mu W 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 1V SiGe Power Amplifier for 81-86 GHz E-band
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3 uW 500 kb/s Ultra Low Power Analog Decoder with Digital I/O in 65 nm CMOS
(2013) International Conference on Electronics and Communication Systems (ICECS)
- Contribution to conference › Paper, not in proceeding
-
Mark
A 0.7 - 3.7 GHz Six Phase Receiver Front-End With Third Order Harmonic Rejection
(2013) IEEE European Solid State Circuits Conference, ESSCIRC 2013
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
(2013)
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Vertical InAs nanowire MOSFETs with IDS = 1.34 mA/µm and gm = 1.19 mS/µm at VDS = 0.5 V
- Contribution to journal › Published meeting abstract
-
Mark
A receiver architecture for devices in wireless body area networks
(2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems
- Contribution to journal › Article
-
Mark
A 65-nm CMOS 250uW Quadrature LO Generation Circuit
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 70 and 210 GHz LO Generator in 65nm CMOS
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A High Efficiency 60GHz Power Amplifier in 65nm CMOS
- Contribution to journal › Published meeting abstract
