Erik Larsson
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- 2004
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A Technique for Optimization of System-on-Chip Test Data Transportation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Student-oriented Examination in a Computer Architecture Course
(
- Contribution to conference › Paper, not in proceeding
- 2003
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimal System-on-Chip Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Resource Partitioning and Optimization for SOC Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Scheduling based on Defect Probability
2003)(
- Other contribution › Miscellaneous