Henrik Sjöland
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- 2012
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Mark
InAs Nanowires for High Frequency Electronics
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
(
- Contribution to journal › Article
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Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
(
- Contribution to journal › Article
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Transistor sizing for a 4-state current mode analog channel decoder in 65-nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A linearized 1.6-5 GHz low noise amplifier using positive feedback in 65 nm CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 65nm CMOS 282uW 915MHz direct conversion receiver front-end
(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 2GHz Tx LO generation circuit with active PPF and 3/2 divider in 65nm CMOS
2011) ISIC 2011 (invited - special session)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding