Pietro Andreani
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- 2017
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Mark
A general theory of phase noise in transconductor-based harmonic oscillators
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- Contribution to journal › Article
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Mark
On the Remarkable Performance of the Series-Resonance CMOS Oscillator
2017) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
A 2.8-3.8-GHz Low-Spur DTC-Based DPLL With a Class-D DCO in 65-nm CMOS
(
- Contribution to journal › Article
- 2016
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Mark
A continuous-time delta-sigma ADC with integrated digital background calibration
(
- Contribution to journal › Article
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Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
(
- Contribution to journal › Article
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Mark
A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration
(
- Contribution to journal › Article
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Mark
A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters
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- Contribution to journal › Article
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Mark
Still More on the 1/f2 Phase Noise Performance of Harmonic Oscillators
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- Contribution to journal › Article
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Mark
A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
(
- Contribution to journal › Article
- 2015
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Mark
A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer
(
- Contribution to journal › Article