Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
(2019) Insulating Films on Semiconductors (INFOS)- Abstract
- We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/816937a5-14db-4df9-8db9-78c88019578a
- author
- Hellenbrand, Markus LU ; Kilpi, Olli-Pekka LU ; Svensson, Johannes LU ; Lind, Erik LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2019-07-02
- type
- Contribution to conference
- publication status
- published
- subject
- keywords
- Low-Frequency Noise, MOSFETs, Nanowires (NWs)
- conference name
- Insulating Films on Semiconductors (INFOS)
- conference location
- Cambridge, United Kingdom
- conference dates
- 2019-06-30 - 2019-07-03
- language
- English
- LU publication?
- yes
- id
- 816937a5-14db-4df9-8db9-78c88019578a
- date added to LUP
- 2019-07-22 10:36:45
- date last changed
- 2020-03-10 17:10:04
@misc{816937a5-14db-4df9-8db9-78c88019578a, abstract = {{We compare III-V nanowire (NW) metal-oxidesemiconductor field-effect transistors (MOSFETs) in a vertical gate-all-around (GAA) as well as a lateral trigate architecture with planar reference MOSFETs and reveal that the NW geometry does not deteriorate the low-frequency noise (LFN) performance. In fact, with gate oxides deposited at the same conditions, the NW structures show potential to achieve better metrics due to slightly lower border trap densities Nbt. The normalized LFN in transistors with a higher number of NW can degrade due to averaging effects between individual nanowires within the same device.}}, author = {{Hellenbrand, Markus and Kilpi, Olli-Pekka and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik}}, keywords = {{Low-Frequency Noise; MOSFETs; Nanowires (NWs)}}, language = {{eng}}, month = {{07}}, title = {{Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs}}, url = {{https://lup.lub.lu.se/search/files/67734229/LFN_Comparison_NW_Planar_III_V_Insight_MHE.pdf}}, year = {{2019}}, }