Scalable Vertical In-Ga-As Nanowire MOSFET With 67 mV/dec at 126μm Gate Width
(2025) In IEEE Electron Device Letters 46(4). p.560-563- Abstract
Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga-As MOSFET with 1600 nanowire channels and 110nm gate length achieved a minimum subthreshold swing of 67 mV/dec at 126μm gate width. The maximum transconductance... (More)
Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga-As MOSFET with 1600 nanowire channels and 110nm gate length achieved a minimum subthreshold swing of 67 mV/dec at 126μm gate width. The maximum transconductance was 0.88mS/μm at 0.5 V drainsource voltage, with 0.22mA/μm normalized drain current. These long-channel results are on par with state-of-the art, but achieved for a device scaled to unprecedented device width. In tandem with the BCB interlayer, these results promise a back-end-of-line compatible high-speed vertical nanowire technology for integration on silicon.
(Less)
- author
- Lofstrand, Anette
LU
; Sandberg, Marcus E.
LU
; Svensson, Johannes LU and Fhager, Lars LU
- organization
- publishing date
- 2025
- type
- Contribution to journal
- publication status
- published
- subject
- keywords
- High-speed devices, III-V on Si, InAs, InGaAs, MOSFET, nanoscale devices, subthreshold swing, transconductance, vertical heterostructure nanowire
- in
- IEEE Electron Device Letters
- volume
- 46
- issue
- 4
- pages
- 4 pages
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:105001544879
- ISSN
- 0741-3106
- DOI
- 10.1109/LED.2025.3535408
- language
- English
- LU publication?
- yes
- id
- ef2281b0-8589-4743-b37e-dd900bed6001
- date added to LUP
- 2025-09-08 12:23:16
- date last changed
- 2025-09-08 12:23:45
@article{ef2281b0-8589-4743-b37e-dd900bed6001, abstract = {{<p>Heterogeneous integration of III-V narrow bandgap transistors on silicon technology is desirable for high frequency circuit implementations. Such high-speed transistors must, however, scale to large gate widths to be suitable for general circuit design. Averaging among many variable channels is a key challenge for nanowire devices. A simplified, but high-speed compatible, nanowire device process was developed here. It utilizes metal plugs to reduce complexity in the gate patterning step. It also implements a spin coated BCB low-k dielectric as top interlayer. A vertical In-Ga-As MOSFET with 1600 nanowire channels and 110nm gate length achieved a minimum subthreshold swing of 67 mV/dec at 126μm gate width. The maximum transconductance was 0.88mS/μm at 0.5 V drainsource voltage, with 0.22mA/μm normalized drain current. These long-channel results are on par with state-of-the art, but achieved for a device scaled to unprecedented device width. In tandem with the BCB interlayer, these results promise a back-end-of-line compatible high-speed vertical nanowire technology for integration on silicon.</p>}}, author = {{Lofstrand, Anette and Sandberg, Marcus E. and Svensson, Johannes and Fhager, Lars}}, issn = {{0741-3106}}, keywords = {{High-speed devices; III-V on Si; InAs; InGaAs; MOSFET; nanoscale devices; subthreshold swing; transconductance; vertical heterostructure nanowire}}, language = {{eng}}, number = {{4}}, pages = {{560--563}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Electron Device Letters}}, title = {{Scalable Vertical In-Ga-As Nanowire MOSFET With 67 mV/dec at 126μm Gate Width}}, url = {{http://dx.doi.org/10.1109/LED.2025.3535408}}, doi = {{10.1109/LED.2025.3535408}}, volume = {{46}}, year = {{2025}}, }