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- 2011
-
Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
(2011) 16th IEEE International Symposium on Asynchronous Circuits and Systems In IET Computers and Digital Techniques 5(4). p.342-353
- Contribution to journal › Article
-
Mark
Developing independence as young academics at LTH
(2011)
- Other contribution › Miscellaneous
-
Mark
Low Power and Area Efficient Implementation of a Real-Time AF Detection Algorithm in 130 nm CMOS
(2011) Swedish System-on-Chip Conference, SSoCC 2011
- Contribution to conference › Paper, not in proceeding
-
Mark
A GALS ASIC implementation from a CAL dataflow description
(2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Synthesis Strategies for Sub-VT Systems
(2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Physical implementation of analog circuits assisted by conventional digital place and route methods
(2011) CDNLive! EMEA, 2011
- Contribution to conference › Other
-
Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
(2011) 29th Norchip conference, 2011
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication
(2010) IEEE Global Telecommunications Conference GLOBECOM 2010
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
