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- 2018
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Mark
A 128 kb 7T SRAM Using a Single-Cycle Boosting Mechanism in 28 nm FD–SOI
(
- Contribution to journal › Article
- 2017
-
Mark
An Area Efficient Single-Cycle xVDD Sub-Vth on-Chip Boost Scheme in 28 nm FD-SOI
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra-low Power Design Approaches in Memories and Assist Techniques
2017)(
- Thesis › Doctoral thesis (compilation)
- 2016
-
Mark
Ultra Low Voltage Synthesizable Memories: A Trade-Off Discussion in 65nm CMOS
(
- Contribution to journal › Article
-
Mark
A 128 Kb Single-Bitline 8.4 fJ/Bit 90MHz at 0.3V 7T Sense-Amplifierless SRAM in 28 nm FD-SOI
2016) European Solid-State Circuits Conference (ESSCIRC). 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low energy and area efficient charge pump with automatic clock controller in 65 nm CMOS
2016) 11th IEEE Asian Solid-State Circuits Conference, A-SSCC 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding