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- 2016
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Mark
III-V heterojunction nanowire tunnel FETs monolithically integrated on silicon
2016) 11th IEEE Nanotechnology Materials and Devices Conference, NMDC 2016(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Lateral InAs/Si p-Type Tunnel FETs Integrated on Si - Part 2 : Simulation Study of the Impact of Interface Traps
(
- Contribution to journal › Article
- 2015
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Mark
Mechanisms of template-assisted selective epitaxy of InAs nanowires on Si
(
- Contribution to journal › Article
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Mark
Template-assisted selective epitaxy of III-V nanoscale devices for co-planar heterogeneous integration with Si
(
- Contribution to journal › Article
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Mark
III-V device integration on Si using template-assisted selective epitaxy
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Vertical InAs-Si gate-all-around tunnel FETs integrated on Si using selective epitaxy in nanotube templates
(
- Contribution to journal › Article
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Mark
Fabrication and analysis of vertical p-type InAs-Si nanowire tunnel FETs
2015) 2015 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon, EUROSOI-ULIS 2015 p.61-64(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
Measurements of light absorption efficiency in InSb nanowires
(
- Contribution to journal › Article
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Mark
Time-Resolved X-ray Diffraction Investigation of the Modified Phonon Dispersion in InSb Nanowires.
(
- Contribution to journal › Article
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Mark
Vertical III-V nanowire device integration on Si(100)
(
- Contribution to journal › Article