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- 2012
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Mark
Ultra Low Power Error Correction Circuits- Technology Scaling and Sub-Vt operation
(
- Contribution to journal › Article
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Mark
High-level energy estimation in the sub-VT domain: simulation and measurement of a cardiac event detector
(
- Contribution to journal › Article
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Mark
IR-Drop Reduction in Sub-VT Circuits by De-synchronization
2012) IEEE Subthreshold Microelectronics Conference, IEEE-Sub-Vt 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
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Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
(
- Contribution to journal › Article
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Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
2011) 16th IEEE International Symposium on Asynchronous Circuits and Systems In IET Computers and Digital Techniques 5(4). p.342-353(
- Contribution to journal › Article
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Mark
Highly Scalable Implementation of a Robust MMSE Channel Estimator for OFDM Multi-Standard Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
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Mark
Energy dissipation reduction of a cardiac event detector in the sub-Vt domain by architectural folding
2010) 19th International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS) 2009 5953. p.347-356(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Design and Measurement of a Variable-Rate Viterbi Decoder in 130-nm Digital CMOS
(
- Contribution to journal › Article
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Mark
Hardware Implementation of an Iterative Sampling Rate Converter for Wireless Communication
2010) IEEE Global Telecommunications Conference GLOBECOM 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding