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- 2012
-
Mark
A 2.45GHz ultra-low power quadrature front-end in 65nm CMOS
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65-nm CMOS 250uW Quadrature LO Generation Circuit
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 70 and 210 GHz LO Generator in 65nm CMOS
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Wideband Reconfigurable Capacitive shunt-feedback LNA in 65nm CMOS
(2012) Norchip conference, 2012
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
(2012) GigaHertz Symposium 2012
- Contribution to conference › Abstract
- 2011
-
Mark
A PLL based 12 GHz LO generator with digital phase control in 90 nm CMOS
- Contribution to journal › Article
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A CMOS 4.35-mW+22-dBm IIP3 Continuously Tunable Channel Select Filter for WLAN/WiMAX Receivers
- Contribution to journal › Article
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
- Contribution to journal › Article
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
