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- 2013
-
Mark
Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In Proceedings - IEEE International Symposium on Circuits and Systems p.1564-1567(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
High-Throughput Hardware-Efficient Soft-Input Soft-Output MIMO Detector for Iterative Receivers
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware Acceleration of the Robust Header Compression (RoHC) Algorithm
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Mapping Channel Estimation and MIMO Detection in LTE-Advanced on a Reconfigurable Cell Array
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A unified multi-mode MIMO detector with soft-output
2012) IEEE International Symposium on Circuits and Systems (ISCAS), 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
Reconfigurable cell array for concurrent support of multiple radio standards by flexible mapping
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding