Syed Muhammad Yasser Sherazi (Former)
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- 2014
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Mark
Ultra low power transceivers for wireless sensors and body area networks
2014) 8th International Symposium on Medical Information and Communication Technology (ISMICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Digital Baseband for Low Power FSK Based Receiver in 65 nm CMOS
2014) IEEE 21th International Conference on Electronics, Circuits and Systems, 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Supply-Voltage Down Conversion for Digital CMOS Designs
2014) IEEE 21th International Conference on Electronics, Circuits and Systems, 2014(
- Contribution to conference › Paper, not in proceeding
- 2013
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
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Mark
Analog and Digital Approaches for an Energy Efficient Low Complexity Channel Decoder
2013) IEEE International Symposium on Circuits and Systems (ISCAS), 2013 In Proceedings - IEEE International Symposium on Circuits and Systems p.1564-1567(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Analog and Digital Design Alternatives for a Low Complexity and Power Constraint Decoder
2013)(
- Contribution to conference › Paper, not in proceeding
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Mark
Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
2013)(
- Thesis › Doctoral thesis (monograph)
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Mark
Two Flavors of 4kb Standard-Cell Based Subvt Memory in 65 nm CMOS
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Savings in Digital Filters for Wireless Communication
2013) European Conference on Circuit Theory and Design (ECCTD 2013)(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
A receiver architecture for devices in wireless body area networks
2012) In IEEE Journal on Emerging and Selected Topics in Circuits and Systems(
- Contribution to journal › Article
-
Mark
Sizing of Dual-V-T Gates for Sub-V-T Circuits
2012) IEEE Subthreshold Microelectronics Conference (SubVT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 100-fJ/cycle Sub-VT Decimation Filter Chain in 65 nm CMOS
2012) IEEE International Conference on Electronics, Circuits, and Systems (ICECS), 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 500 fW/bit 14 fJ/bit-access 4kb Standard-Cell Based Sub-VT Memory in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integration of Full-Custom Cells in a Standard-Cell Based Flow
2012) CDNLive! EMEA, 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
(
- Contribution to journal › Article
-
Mark
Synthesis Strategies for Sub-VT Systems
2011) 20th European Conference on Circuit Theory and Design. ECCTD 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Impact of switching activity on the energy minimum voltage for 65 nm Sub-VT CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Physical implementation of analog circuits assisted by conventional digital place and route methods
2011) CDNLive! EMEA, 2011(
- Contribution to conference › Other