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- 2014
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Mark
Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems
(
- Contribution to journal › Article
- 2011
-
Mark
Adaptive Execution Assistance for Multiplexed Fault-Tolerant Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
- 2010
-
Mark
Test Scheduling of Modular System-on-Chip under Capture Power Constraint
2010) IEEE Eleventh Workshop on RTL and High Level Testing, 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Energy-Efficient Fault Tolerance in Chip Multiprocessors Using Critical Value Forwarding
2010) The 40th Annual IEEE/IFIP International Conference on Dependable Systems and Networks (DSN'10)Chicago, Illinois, USA, June 28-July 1, 2010. p.121-130(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Multiplexed redundant execution: A technique for efficient fault tolerance in chip multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Graph Theoretic Approach for Scan Cell Reordering to Minimize Peak Shift Power
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Energy-Efficient Redundant Execution for Chip Multiprocessors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scan Cells Reordering to Minimize Peak Power During Test Cycle : A Graph Theoretic Approach
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2010) IEEE East-West Design and Test Symposium (EWDTS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
Fault-Tolerant Average Execution Time Optimization for System-On-Chips
2009) Frontiers of High Performance Embedded Computing(
- Contribution to conference › Paper, not in proceeding
-
Mark
Thermal Aware Test Scheduling for Stacked Multi-Chip-Modules
2009) DATE 2009 Friday Workshop on 3D Integration - Technology, Architecture, Design, Automation, and Tes(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Efficient Redundant Execution for Chip Multiprocessors
(
- Contribution to conference › Paper, not in proceeding
-
Mark
An Even-Odd DFD Technique for Scan Chain Diagnosis
2009) Workshop on RTL and High Level Testing (WRTLT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Capture Power Reduction for Modular System-on-Chip Test
2009) IEEE/VSI VLSI Design and Test Symposium (VDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
On Minimization of Peak Power for Scan Circuit during Test
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scan Cell Reordering to Minimize Peak Power during Scan Testing of SoC
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Generation of Minimal Leakage Input Vectors with Constrained NBTI Degradation
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
On Reduction of Capture Power for Modular System-on-Chip Test
2008) IEEE Workshop on RTL and High Level Testing WRTLT08(
- Contribution to conference › Paper, not in proceeding