Elvedin Memisevic (Former)
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- 2017
-
Mark
The impact of hetero-junction and oxide-interface traps on the performance of InAs/Si and InAs/GaAsSb nanowire tunnel FETs
(2017) 2017 International Conference on Simulation of Semiconductor Processes and Devices, SISPAD 2017 2017-September. p.273-276
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
InAs/GaSb vertical nanowire TFETs on Si for digital and analogue applications
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
- Contribution to journal › Letter
- 2015
-
Mark
Vertical InAs/GaSb Nanowire Axial TFETs Integrated on Si-substrates
(2015) Compound Semiconductor Week 2015
- Contribution to conference › Paper, not in proceeding
-
Mark
III-V Heterostructure Nanowire Tunnel FETs
- Contribution to journal › Article
- 2014
-
Mark
High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates
- Contribution to journal › Article
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Mark
RF Characterization of Vertical InAs Nanowire MOSFETs with f(t) and f(max) above 140 GHz
(2014) 26th International Conference on Indium Phosphide and Related Materials (IPRM)
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Thin electron beam defined hydrogen silsesquioxane spacers for vertical nanowire transistors
- Contribution to journal › Article
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