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Test Planning and Test Access Mechanism Design for Stacked Chips using ILP

Sengupta, Breeta LU and Larsson, Erik LU (2014) IEEE VLSI Test Symposium (VTS) In VLSI Test Symposium (VTS), 2014 IEEE 32nd p.1-6
Abstract
In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results

show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Chapter in Book/Report/Conference proceeding
publication status
published
subject
keywords
DfT (Design for test), Test Architecture, Scan chain, Wrapper Chain, Test Scheduling, Test Time., 3D Stacked Integrated Circuit (SIC), Integer Linear Programming (ILP)
in
VLSI Test Symposium (VTS), 2014 IEEE 32nd
pages
6 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
conference name
IEEE VLSI Test Symposium (VTS)
external identifiers
  • wos:000342177000020
  • scopus:84901947022
ISSN
1093-0167
DOI
10.1109/VTS.2014.6818764
language
English
LU publication?
yes
id
9a81768d-2af8-458a-9ab3-1f6db6344bc4 (old id 4302313)
alternative location
http://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=6818764&tag=1
date added to LUP
2014-02-13 10:48:30
date last changed
2017-01-01 06:31:06
@inproceedings{9a81768d-2af8-458a-9ab3-1f6db6344bc4,
  abstract     = {In this paper we propose a scheme for test planning and test access mechanism (TAM) design for stacked integrated circuits (SICs) that are designed in a core-based manner. Our scheme minimizes the test cost, which is given as the weighted sum of the test time and the TAM width. The test cost is evaluated for a test flow that consists of a wafer sort test of each individual chip and a package test of the complete stack of chips. We use an Integer Linear Programming (ILP) model to find the optimal test cost. The ILP model is implemented on several designs constructed from ITC’02 benchmarks. The experimental results<br/><br>
show significant reduction in test cost compared to when using schemes, which are optimized for non-stacked chips.},
  author       = {Sengupta, Breeta and Larsson, Erik},
  booktitle    = {VLSI Test Symposium (VTS), 2014 IEEE 32nd},
  issn         = {1093-0167},
  keyword      = {DfT (Design for test),Test Architecture,Scan chain,Wrapper Chain,Test Scheduling,Test Time.,3D Stacked Integrated Circuit (SIC),Integer Linear Programming (ILP)},
  language     = {eng},
  pages        = {1--6},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  title        = {Test Planning and Test Access Mechanism Design for Stacked Chips using ILP},
  url          = {http://dx.doi.org/10.1109/VTS.2014.6818764},
  year         = {2014},
}