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Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si

Berg, Martin LU ; Kilpi, Olli-Pekka LU ; Persson, Karl-Magnus LU ; Svensson, Johannes LU ; Hellenbrand, Markus LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2016) In IEEE Electron Device Letters 37(8). p.966-969
Abstract
Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
vertical, nanowire, InAs, MOSFET, transistor, gate-last, self-aligned
in
IEEE Electron Device Letters
volume
37
issue
8
pages
4 pages
publisher
IEEE--Institute of Electrical and Electronics Engineers Inc.
external identifiers
  • scopus:84982719298
  • wos:000380330000005
ISSN
0741-3106
DOI
10.1109/LED.2016.2581918
language
English
LU publication?
yes
id
5a9dc9e4-23e3-426b-8bee-85e40faa56e4
date added to LUP
2016-09-15 09:27:56
date last changed
2017-03-06 10:38:26
@article{5a9dc9e4-23e3-426b-8bee-85e40faa56e4,
  abstract     = {Vertical InAs nanowire transistors are fabricated on Si using a gate-last method, allowing for lithography-based control of the vertical gate length. The best devices combine good ON- and OFF-performance, exhibiting an ON-current of 0.14 mA/μm, and a sub-threshold swing of 90 mV/dec at 190 nm LG. The device with the highest transconductance shows a peak value of 1.6 mS/μm. From RF measurements, the border trap densities are calculated and compared between devices fabricated using the gate-last and gate-first approaches, demonstrating no significant difference in trap densities. The results thus confirm the usefulness of implementing digital etching in thinning down the channel dimensions.},
  author       = {Berg, Martin and Kilpi, Olli-Pekka and Persson, Karl-Magnus and Svensson, Johannes and Hellenbrand, Markus and Lind, Erik and Wernersson, Lars-Erik},
  issn         = {0741-3106},
  keyword      = {vertical,nanowire,InAs,MOSFET,transistor,gate-last,self-aligned},
  language     = {eng},
  month        = {08},
  number       = {8},
  pages        = {966--969},
  publisher    = {IEEE--Institute of Electrical and Electronics Engineers Inc.},
  series       = {IEEE Electron Device Letters},
  title        = {Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si},
  url          = {http://dx.doi.org/10.1109/LED.2016.2581918},
  volume       = {37},
  year         = {2016},
}