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- 2021
-
Mark
Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications
(2021)
- Thesis › Doctoral thesis (compilation)
-
Mark
Increased Breakdown Voltage in Vertical Heterostructure III-V Nanowire MOSFETs with a Field Plate
- Contribution to journal › Article
- 2020
-
Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
- Contribution to journal › Article
- 2019
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
- Contribution to journal › Article
-
Mark
Vertical III-V Nanowire MOSFETs
(2019) In Series of licentiate and doctoral theses
- Thesis › Doctoral thesis (compilation)
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
- Contribution to journal › Article
- 2017
-
Mark
Vertical III-V Nanowire Tunnel Field-Effect Transistor
(2017)
- Thesis › Doctoral thesis (compilation)
- 2016
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
- Contribution to journal › Letter
- 2015
-
Mark
Vertical InAs Nanowire Devices and RF Circuits
- Thesis › Doctoral thesis (compilation)
- 2007
-
Mark
Statistical rate allocation for layered space-time structure
- Contribution to journal › Article
