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Vertical III-V Nanowire Tunnel Field-Effect Transistor

Memisevic, Elvedin LU (2017)
Abstract
In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel... (More)
In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-κ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I60 of 0.31 μA/μm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I60, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices. (Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Professor Miyamoto, Yasuyuki, Tokyo Institute of Technology, Tokyo, Japan
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Transistor, TFET, Steep slope, Nanowire, III-V materials, HSQ, Vertical, InAs, GaSb, MOSFET
publisher
The Department of Electrical and Information Technology
defense location
Lecture hall E:1406, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund
defense date
2017-09-14 10:15
ISBN
978-91-7753-254-5
language
English
LU publication?
yes
id
c40eab84-1f8f-469b-bc64-889e9514f4d0
date added to LUP
2017-08-21 08:39:32
date last changed
2017-09-11 07:02:28
@phdthesis{c40eab84-1f8f-469b-bc64-889e9514f4d0,
  abstract     = {In this thesis fabrication and optimization of vertical III-V Tunneling Field-Effect transistors was explored. Usage of vertical nanowires, allows for combination of materials with large lattice mismatch in the same nanowire structure. TFETs in this thesis were fabricated using vertical InAs/GaSb or InAs/InGaAsSb/GaSb nanowires of high material quality. Usage of these  material systems allowed for fabrication of devices with staggered and broken band-gap alignment. To fully harvest the benefits from these structures, the fabrication process was optimized. This was performed by exploring different spacer and gate technologies, required for vertical devices. Furthermore, improvement of electrostatics was achieved by reduction of the channel diameter and high-κ interface. Further improvements of the performance were achieved by scaling of the device dimensions such as nanowire lengths, spacer thickness, and gate-length. Used fabrication techniques allowed us to fabricate devices with a channel diameter of 11 nm. By switching from InAs/GaSb to InAs/InGaAsSb/GaSb allowed for optimization of the heterojunction, which allowed us to fabricate devices with record performance, reaching a minimum subthreshold swing of 48 mV/decade and a record high I<sub>60</sub> of 0.31 μA/μm at a drive voltage of 0.3 V. Stability of the process allowed us to demonstrate data from a large number of TFETs with ability to operate below the thermal limit of 60 mV/decade. This allowed us to study correlations between important device parameter such as: I<sub>60</sub>, on-current, subthreshold swing, and off-current. Using transmission electron microscopy, the heterojunction was characterized. Furthermore, TCAD modeling was performed to understand what limits the performance of these devices. Also, electrical measurement of the random telegraph noise allowed us to understand the impact the oxide defects have on highly scaled devices.},
  author       = {Memisevic, Elvedin},
  isbn         = {978-91-7753-254-5},
  keyword      = {Transistor,TFET,Steep slope,Nanowire,III-V materials,HSQ,Vertical,InAs,GaSb,MOSFET},
  language     = {eng},
  month        = {08},
  publisher    = {The Department of Electrical and Information Technology},
  school       = {Lund University},
  title        = {Vertical III-V Nanowire Tunnel Field-Effect Transistor},
  year         = {2017},
}