Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon
(2022) In IEEE Electron Device Letters 43(6). p.854-857- Abstract
- We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.
Please use this url to cite or link to this publication:
https://lup.lub.lu.se/record/816728fc-0179-44b8-a55f-d961eae1417b
- author
- Persson, Anton E. O. LU ; Zhu, Zhongyunshen LU ; Athle, Robin LU and Wernersson, Lars-Erik LU
- organization
- publishing date
- 2022-06
- type
- Contribution to journal
- publication status
- published
- subject
- in
- IEEE Electron Device Letters
- volume
- 43
- issue
- 6
- pages
- 854 - 857
- publisher
- IEEE - Institute of Electrical and Electronics Engineers Inc.
- external identifiers
-
- scopus:85129367060
- ISSN
- 0741-3106
- DOI
- 10.1109/LED.2022.3171597
- language
- English
- LU publication?
- yes
- id
- 816728fc-0179-44b8-a55f-d961eae1417b
- date added to LUP
- 2022-05-30 14:47:02
- date last changed
- 2024-02-01 15:15:10
@article{816728fc-0179-44b8-a55f-d961eae1417b, abstract = {{We demonstrate a successful process scheme for the integration of a CMOS-compatible ferroelectric gate stack on a scaled vertical InAs nanowire gate-all-around MOSFET on silicon. The devices show promising device characteristics with nanosecond write time and large memory window of >1.5 V. In the current implementation, the device performance is mainly limited by access resistance, which is attributed to the thermal sensitivity of InAs. The findings indicate that the ferroelectricity is not intrinsically preventing future improvements of scaled III-V FeFETs.}}, author = {{Persson, Anton E. O. and Zhu, Zhongyunshen and Athle, Robin and Wernersson, Lars-Erik}}, issn = {{0741-3106}}, language = {{eng}}, number = {{6}}, pages = {{854--857}}, publisher = {{IEEE - Institute of Electrical and Electronics Engineers Inc.}}, series = {{IEEE Electron Device Letters}}, title = {{Integration of Ferroelectric HfxZr1-xO2 on Vertical III-V Nanowire Gate-All-Around FETs on Silicon}}, url = {{https://lup.lub.lu.se/search/files/119233421/FINAL_VERSION.PDF.pdf}}, doi = {{10.1109/LED.2022.3171597}}, volume = {{43}}, year = {{2022}}, }