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- 2019
-
Mark
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2017
-
Mark
Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at VDS = 0.3 V
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
(
- Contribution to journal › Letter
- 2014
-
Mark
High-Frequency Gate-All-Around Vertical InAs Nanowire MOSFETs on Si Substrates
(
- Contribution to journal › Article
-
Mark
RF Characterization of Vertical InAs Nanowire MOSFETs with f(t) and f(max) above 140 GHz
2014) 26th International Conference on Indium Phosphide and Related Materials (IPRM)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Thin electron beam defined hydrogen silsesquioxane spacers for vertical nanowire transistors
(
- Contribution to journal › Article