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- 2019
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
- 2018
-
Mark
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2017
-
Mark
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μa/μm at Ioff = 100 nA/μm and VD = 0.5 v
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Low-Frequency Noise in III-V Nanowire TFETs and MOSFETs
2017) In IEEE Electron Device Letters(
- Contribution to journal › Letter
-
Mark
Vertical InAs/InGaAs Heterostructure Metal-Oxide-Semiconductor Field-Effect Transistors on Si
(
- Contribution to journal › Article
- 2016
-
Mark
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
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