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- 2014
-
Mark
A 35 fJ/bit-access Sub-VT Memory Using a Dual-Bit Area-Optimized Standard-cell in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra low power transceivers for wireless sensors and body area networks
2014) 8th International Symposium on Medical Information and Communication Technology (ISMICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Hardware Efficient Approximative Matrix Inversion for Linear Pre-Coding in Massive MIMO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65 nm Single Stage 28 fJ/cycle 0.12 to 1.2V Level-Shifter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.28-0.8 V 320 fW D-latch for Sub-VT Memories in 65 nm CMOS
2014) FTFC(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-complex peak-to-average power reduction scheme for OFDM based massive MIMO systems
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Lessons from Ten Years of the International Master’s Program in System-on-Chip
2014) The 10th European Workshop on Microelectronics Education (EWME 2014)(
- Contribution to conference › Paper, not in proceeding
- 2013
-
Mark
Dual-VT 4kb Sub-VT Memories with <1 pW/bit Leakage in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
-
Mark
Next Generation Digital Front-End for Multi-Standard Concurrent Reception
2013) NORCHIP Conference, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding