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- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2017
-
Mark
Ultra-wideband transmitter design based on a new transmitted reference pulse cluster
(
- Contribution to journal › Article
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
2017)(
- Thesis › Doctoral thesis (monograph)
- 2016
-
Mark
Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
2016)(
- Thesis › Doctoral thesis (compilation)
-
Mark
A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
(
- Contribution to journal › Article
- 2015
-
Mark
III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si
(
- Contribution to journal › Article
-
Mark
A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
Continuous-Time Delta-Sigma Modulators for Wireless Communication
2014) In Series of licentiate and doctoral dissertations(
- Thesis › Doctoral thesis (compilation)
-
Mark
A Class-D CMOS DCO with an on-chip LDO
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Miniaturized Marchand Balun in CMOS With Improved Balance for Millimeter-Wave Applications
(
- Contribution to journal › Article