Ping Lu (Former)
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- 2017
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Mark
Ultra-wideband transmitter design based on a new transmitted reference pulse cluster
(
- Contribution to journal › Article
- 2016
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Mark
A 2.2ps 2-D Gated-Vernier Time-to-Digital Converter with Digital Calibration
(
- Contribution to journal › Article
-
Mark
A wide band fractional-N digital PLL with a noise shaping 2-D time to digital converter for LTE-A applications
(
- Contribution to journal › Article
-
Mark
A 3.5-6.8GHz wide-bandwidth DTC-assisted fractional-N all-digital PLL with a MASH ΔΣ TDC for low in-band phase noise
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2015
-
Mark
A 103fsrms 1.32mW 50MS/s 1.25MHz Bandwidth Two-Step Flash-ΔΣ Time-to-Digital Converter for ADPLL
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 65nm CMOS fraction-N digital PLL with shaped in-band phase noise
2015) Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 9-bit 1-MS/s 7-μW SAR ADC for ultra low power radio
2015) 32nd NORCHIP Conference, 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
A 1-1 MASH 2-D Vernier Time-to-Digital Converter with 2nd-order noise shaping
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A LC Quadrature VCO With WideTuningRange For TRPC-UWB Application in 0.13-µm CMOS
2014) IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A TRPC-UWB Transmitter Front-end Based on Wideband IQ Modulator in 0.13-µm CMOS
2014) IEEE 12th International Conference on Solid-State and Integrated Circuit Technology (ICSICT)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Contribution to journal › Article
-
Mark
A 2-D GRO Vernier Time-to-Digital Converter with Large Input Range and Small Latency
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Wide Bandwidth Fractional-N Synthesizer for LTE with Phase Noise Cancellation Using a Hybrid- -DAC and Charge Re-timing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based 2-Dimension Vernier Time-to-Digital Converter
2013) Norchip conference, 2012(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A 90nm CMOS Digital PLL Based on Vernier-Gated-Ring-Oscillator Time-to-Digital Converter
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3.6mW, 90nm CMOS Gated-Vernier Time-to-Digital Converter with an Equivalent Resolution of 3.2ps
(
- Contribution to journal › Article
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract
- 2011
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
A mixed mode design flow for multi GHz ADPLLs
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 90nm CMOS Gated-Ring-Oscillator-Based Vernier Time-to-Digital Converter with Improved Resolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Digital PLL with a Multi-Delay Coarse-Fine TDC
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 0.13µm CMOS ΔΣ PLL FM Transmitter
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 2.7GHz divider-less all digital phase-locked loop with 625Hz frequency resolution in 90nm CMOS
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
A High-resolution Vernier Gated-Ring-Oscillator TDC in 90-nm CMOS
2010) NORCHIP Conference, 2010(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2009
-
Mark
A 5.4GHz wide tuning range CMOS PLL using an auto-calibration multiple-pass ring oscillator
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
A 5.4GHz 90-nm CMOS digitally controlled LC oscillator with 21% tuning range, 1.1MHz resolution, and 180dB FOM
2008) Norchip Conference, 2008(
- Contribution to conference › Paper, not in proceeding
- 2007
-
Mark
A low-jitter clock generator for HDTV
(
- Contribution to journal › Article
-
Mark
A 4 GHz ring oscillator based on dual-feedback loops with PVT deviation adaption
(
- Contribution to journal › Article
- 2006
-
Mark
A 12-bit 125-MHz segmented current-steering DAC for communication application
2006) The IET International Conference on Wireless, Mobile and Multimedia Networks(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 4.6GHz PLL with automatic frequency calibration based on multiple-pass ring oscillator
2006) The IET International Conference on Wireless, Mobile and Multimedia Networks(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-jitter frequency synthesizer with dynamic phase interpolation for high-speed Ethernet
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A low-jitter and low-power frequency synthesizer applied to 1000 Base-T Ethernet
(
- Contribution to journal › Article
- 2005
-
Mark
A 3.3v low-jitter frequency Synthesizer applied to fast Ethernet transceiver
(
- Contribution to journal › Article
-
Mark
Delay-locked loop and its applications
(
- Contribution to journal › Article
-
Mark
A 1.8v low-jitter clock generator for 1000 Base-T Ethernet Transceiver
(
- Contribution to journal › Article
-
Mark
A 1.8V transmitter for 10/100 Mbps Ethernet physical layer
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 3.3V low-jitter frequency synthesizer applied to fast Ethernet transceiver
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 1997
-
Mark
Polycrystalline germanium dioxide hollow-core fibers and their performance
(
- Contribution to journal › Article