1 – 33 of 33
- show: 50
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2017
-
Mark
Test Planning for Core-based Integrated Circuits under Power Constraints
(
- Contribution to journal › Article
- 2015
-
Mark
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
(
- Contribution to journal › Article
- 2014
-
Mark
Evaluation of Level of Confidence and Optimization of Roll-back Recovery with Checkpointing for Real-Time Systems
(
- Contribution to journal › Article
-
Mark
Fault injection and fault handling: an MPSoC demonstrator using IEEE P1687
2014) 20th IEEE International On-Line Testing Symposium(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Contribution to journal › Article
-
Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Reusing and Retargeting On-Chip Instrument Access Procedures in IEEE P1687
(
- Contribution to journal › Article
-
Mark
Access Time Analysis for IEEE P1687
(
- Contribution to journal › Article
-
Mark
An MPSoCs demonstrator for fault injection and fault handling in an IEEE P1687 environment
2012) IEEE European Test Symposium (ETS), 2012(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Planning for 3D Stacked ICs with Through-Silicon Vias
2011) Second IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling and Test Access Optimization for Core-Based 3D Stacked ICs with Through-Silicon Vias: poster
2011) IEEE European Test Symposium (ETS), 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Measurement Point Selection for In-Operation Wear-Out Monitoring
2011) 14th IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems (DDECS11)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Level of Confidence Evaluation and Its Usage for Roll-back Recovery with Checkpointing Optimization
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Study on the Level of Confidence for Roll-back Recovery with Checkpointing
2011) 1st Intl. Workshop on Dependability Issues in Deep-submicron Technologies (DDT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Design Automation for IEEE P1687
2011) Design, Automation and Test in Europe (DATE 2011),(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Study of Instrument Reuse and Retargeting in P1687
2011) IEEE Twelfth Workshop on RTL and High Level Testing (WRTLT 2011)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Power Constrained Test Scheduling for 3D Stacked Chips: poster
2010) 1st IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits(
- Contribution to conference › Poster
-
Mark
Study on Combined Test-Data Compression and Test Planning for Testing of Modular SoCs
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Estimating Error-Probability and Its Application for Optimizing Roll-back Recovery with Checkpointing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
On-line Techniques to Adjust and Optimize Checkpointing Frequency
2010) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2010) p.29-33(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Time Analysis for IEEE P1687
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test scheduling on IJTAG
2010) Nordic Test Forum (NTF 2010),(
- Contribution to conference › Paper, not in proceeding
-
Mark
Optimizing Fault Tolerance for Multi-Processor System-on-Chip
2010)(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Efficient Embedding of Deterministic Test Data
2010) 19th IEEE Asian Test Symposium (ATS10)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Mapping and Scheduling of Jobs in Homogeneous NoC-based MPSoC
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
-
Mark
Efficient Embedding of Deterministic Test Data
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
- 2005
-
Mark
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding