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- 2020
-
Mark
Design of an area efficient crypto processor for 3GPP-LTE NB-IoT devices
(
- Contribution to journal › Article
- 2018
-
Mark
On-Chip Fault Monitoring Using Self-Reconfiguring IEEE 1687 Networks
(
- Contribution to journal › Article
- 2017
-
Mark
A transmission line model for co-designed slot-coupled dielectric resonator antennas
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Low power analog channel decoder in sub-threshold 65nm CMOS
2010) Swedish System-on-Chip Conference 2010 (SSoCC'10)(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Architecture for Integrated Test Data Compression and Abort-on-Fail Testing in a Multi-Site Environment
(
- Contribution to journal › Article
-
Mark
A variable-rate Viterbi decoder in 130-nm CMOS: design, measurements, and cost of flexibility
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Protocol Requirements in an SJTAG/IJTAG Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding