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- 2015
-
Mark
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
(
- Contribution to journal › Article
- 2008
-
Mark
An Integrated System-on-Chip Test Framework
2008) p.439-454(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2007) p.221-244(
- Chapter in Book/Report/Conference proceeding › Book chapter
-
Mark
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimized Integration of Test Compression and Sharing for SOC Testing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2005
-
Mark
SOC Test Scheduling with Test Set Sharing and Broadcasting
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Silent CMOS circuits aiming for system-on-chip
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Introduction to Advanced System-on-Chip Test Design and Optimization
2005) In Frontiers in Electronic Testing(
- Book/Report › Book
-
Mark
Multiple Constraints Driven System-on-Chip Test Time Optimization
(
- Contribution to journal › Article
-
Mark
Automatic generation of application-specific systems based on a micro-programmed Java core
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2004
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Technique for Optimization of System-on-Chip Test Data Transportation
(
- Contribution to conference › Paper, not in proceeding
-
Mark
Defect-Aware SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2003
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Efficient Approach to SoC Wrapper Design, TAM Configuration and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Scheduling based on Defect Probability
2003)(
- Other contribution › Miscellaneous
-
Mark
Defect Probability-based System-On-Chip Test Scheduling
2003) 6th IEEE International Workshop on Design and Diagnostics of Electronics Circuits and Systems DDECS 03,2003 p.25-32(
- Contribution to conference › Paper, not in proceeding
- 2002
-
Mark
A direct digital RF amplitude modulator
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
2002) p.21-36(
- Chapter in Book/Report/Conference proceeding › Book chapter
- 2001
-
Mark
The Design and Optimization of SOC Test Solutions
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated System-On-Chip Test Framework
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2000
-
Mark
An Integrated System-Level Design for Testability Methodology An Integrated System-Level Design for Testability Methodology
2000)(
- Thesis › Doctoral thesis (monograph)