Integrated Electronic Systems
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- 2020
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Mark
Test Cost Reduction of 3D Stacked ICs : Test Planning and Test Flow Selection
2020)(
- Thesis › Doctoral thesis (monograph)
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Mark
An N-Path Filter Design Methodology With Harmonic Rejection, Power Reduction, Foldback Elimination, and Spectrum Shaping
2020) In IEEE Transactions on Circuits and Systems I: Regular Papers(
- Contribution to journal › Article
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Mark
Enabling Image Recognition on Constrained Devices Using Neural Network Pruning and a CycleGAN
2020) First international workshop on Internet of Things for Emergency Management (IoT4Emergency)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Analysis and Design of a 17-GHz All-npn Push-Pull Class-C VCO
(
- Contribution to journal › Article
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Mark
A 20-GHz Bandwidth Power Amplifier for Phased Array 5G New Radio Transmitters
(
- Contribution to journal › Article
- 2019
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Mark
A Low Latency FFT/IFFT Architecture for Massive MIMO Systems Utilizing OFDM Guard Bands
(
- Contribution to journal › Article
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Mark
Impact of Relay Cooperation on the Performance of Large-Scale Multipair Two-Way Relay Networks
2019) 2018 IEEE Global Communications Conference, GLOBECOM 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Fully Decentralized Massive MIMO Detection Based on Recursive Methods
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
(
- Contribution to journal › Article
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Mark
An Injection-Locked Power Up-Converter in 65-nm CMOS for Cellular Applications
(
- Contribution to journal › Article