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Low-Frequency Noise in Nanowire and Planar III-V MOSFETs

Hellenbrand, Markus LU ; Kilpi, Olli-Pekka LU ; Svensson, Johannes LU ; Lind, Erik LU and Wernersson, Lars-Erik LU (2019) In Microelectronic Engineering
Abstract
Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is... (More)
Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four. (Less)
Please use this url to cite or link to this publication:
author
organization
publishing date
type
Contribution to journal
publication status
published
subject
keywords
III-V, Nanowire (NW), MOSFET, Low-Frequency Noise, Gate Oxide Defects, Border Traps
in
Microelectronic Engineering
publisher
Elsevier
external identifiers
  • scopus:85067844868
ISSN
0167-9317
DOI
10.1016/j.mee.2019.110986
language
English
LU publication?
yes
id
ca27c63d-2516-49df-a9c5-463674963fa0
date added to LUP
2019-05-20 11:33:59
date last changed
2019-07-22 13:14:13
@article{ca27c63d-2516-49df-a9c5-463674963fa0,
  abstract     = {Nanowire geometries are leading contenders for future low-power transistor design. In this study, low-frequency noise is measured and evaluated in highly scaled III-V nanowire metal-oxide-semiconductor field-effect transistors (MOSFETs) and in planar III-V MOSFETs to investigate to what extent the device geometry affects the noise performance. Number fluctuations are identified as the dominant noise mechanism in both architectures. In order to perform a thorough comparison of the two architectures, a discussion of the underlying noise model is included. We find that the noise performance of the MOSFETs in a nanowire architecture is at least comparable to the planar devices. The input-referred voltage noise in the nanowire devices is superior by at least a factor of four.},
  articleno    = {110986},
  author       = {Hellenbrand, Markus and Kilpi, Olli-Pekka and Svensson, Johannes and Lind, Erik and Wernersson, Lars-Erik},
  issn         = {0167-9317},
  keyword      = {III-V,Nanowire (NW),MOSFET,Low-Frequency Noise,Gate Oxide Defects,Border Traps},
  language     = {eng},
  month        = {05},
  publisher    = {Elsevier},
  series       = {Microelectronic Engineering},
  title        = {Low-Frequency Noise in Nanowire and Planar III-V MOSFETs},
  url          = {http://dx.doi.org/10.1016/j.mee.2019.110986},
  year         = {2019},
}