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- 2019
-
Mark
Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
(2019) In Microelectronic Engineering
- Contribution to journal › Article
-
Mark
Comparison of Low-Frequency Noise in Nanowire and Planar III-V MOSFETs
(2019) Insulating Films on Semiconductors (INFOS)
- Contribution to conference › Paper, not in proceeding
-
Mark
Reducing ambipolar off-state leakage currents in III-V vertical nanowire tunnel FETs using gate-drain underlap
- Contribution to journal › Article
- 2018
-
Mark
CMOS Integration Based on All-III-V Materials
(2018) Swedish Microwave Days 2018
- Contribution to conference › Abstract
-
Mark
Vertical, High-Performance 12 nm diameter InAs Nanowire MOSFETs on Si using an all III-V CMOS process
(2018) Compound Semiconductor Week 2018
- Contribution to conference › Abstract
-
Mark
Impact of source doping on the performance of vertical InAs/InGaAsSb/GaSb nanowire Tunnel Field-Effect Transistors
- Contribution to journal › Article
-
Mark
Sub-100-nm gate-length scaling of vertical InAs/InGaAs nanowire MOSFETs on Si
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
- Contribution to journal › Article
-
Mark
RF Characterisation of Vertical III-V Nanowire Tunnel FETs
(2018) Swedish Microwave Days 2018
- Contribution to conference › Paper, not in proceeding
-
Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
- Contribution to journal › Article
