21 – 30 of 75
- show: 10
- |
- sort: year (new to old)
Close
Embed this list
<iframe src=" "
width=" "
height=" "
allowtransparency="true"
frameborder="0">
</iframe>
- 2013
-
Mark
Design Space Exploration of Digital Circuits for Ultra-low Energy Dissipation
2013)(
- Thesis › Doctoral thesis (monograph)
-
Mark
Highly Efficient Class-C CMOS VCOs, Including a Comparison With Class-B VCOs
(
- Contribution to journal › Article
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
-
Mark
Receiver Front-Ends in CMOS with Ultra-Low Power Consumption
2013)(
- Thesis › Doctoral thesis (compilation)
-
Mark
Class-D CMOS Oscillators
(
- Contribution to journal › Article
- 2012
-
Mark
An Analysis of 1/f Noise to Phase Noise Conversion in CMOS Harmonic Oscillators
(
- Contribution to journal › Article
- 2011
-
Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article
-
Mark
Micro- and Millimeter Wave CMOS Beamforming Receivers
2011)(
- Thesis › Doctoral thesis (compilation)