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- 2020
-
Mark
A Decade Frequency Range CMOS Power Amplifier for Sub-6-GHz Cellular Terminals
(
- Contribution to journal › Article
- 2019
-
Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
(
- Contribution to journal › Article
- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2014
-
Mark
A Miniaturized Marchand Balun in CMOS With Improved Balance for Millimeter-Wave Applications
(
- Contribution to journal › Article
-
Mark
Lessons from Ten Years of the International Master’s Program in System-on-Chip
2014) The 10th European Workshop on Microelectronics Education (EWME 2014)(
- Contribution to conference › Paper, not in proceeding
- 2013
-
Mark
A 0.7 to 3 GHz wireless receiver front end in 65-nm CMOS with an LNA linearized by positive feedback
(
- Contribution to journal › Article
-
Mark
Ultra Low Energy Design Exploration of Digital Decimation Filters in 65 nm Dual-VT CMOS in the Sub-VT Domain
(
- Contribution to journal › Article
- 2011
-
Mark
Design and analysis of an ultra-low-power LC quadrature VCO
(
- Contribution to journal › Article
-
Mark
A 1.6-2.6GHz 29dBm Injection-Locked Power Amplifier with 64% peak PAE in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 5GHz 90-nm CMOS all digital phase-locked loop
(
- Contribution to journal › Article