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- 2020
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
(
- Contribution to journal › Article
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Mark
Embedded sacrificial AlAs segments in GaAs nanowires for substrate reuse
(
- Contribution to journal › Article
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Mark
Electrical Characterisation of III-V Nanowire MOSFETs
2020) In Series of Licentiate and Doctoral Theses(
- Thesis › Doctoral thesis (compilation)
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
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Mark
Implementing an Insect Brain Computational Circuit Using III-V Nanowire Components in a Single Shared Waveguide Optical Network
(
- Contribution to journal › Article
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Mark
Self-Limiting Polymer Exposure for Vertical Processing of Semiconductor Nanowire-Based Flexible Electronics
(
- Contribution to journal › Article
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Mark
Direct Three-Dimensional Imaging of an X-ray Nanofocus Using a Single 60 nm Diameter Nanowire Device
(
- Contribution to journal › Article
- 2019
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Mark
Transition to the quantum hall regime in InAs nanowire cross-junctions
(
- Contribution to journal › Article
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Mark
Dimension Engineering of High-Quality InAs Nanostructures on a Wafer Scale
(
- Contribution to journal › Article
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Mark
Simulation of GaAs Nanowire Growth and Crystal Structure
(
- Contribution to journal › Article