Digital ASIC-lup-obsolete
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- 2011
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Mark
Multicarrier faster-than-Nyquist transceivers: hardware architecture and performance analysis
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- Contribution to journal › Article
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Mark
Benchmarking of Standard-Cell Based Memories in the sub-VT Domain in 65-nm CMOS Technology
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- Contribution to journal › Article
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Mark
Energy-minimum sub-threshold self-timed circuits using current sensing completion detection
2011) 16th IEEE International Symposium on Asynchronous Circuits and Systems In IET Computers and Digital Techniques 5(4). p.342-353(
- Contribution to journal › Article
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Mark
Design exploration of a 65 nm Sub-VT CMOS digital decimation filter chain
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Diameter reduction of nanowire tunnel heterojunctions using in situ annealing
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- Contribution to journal › Article
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Mark
Guest Editorial
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- Contribution to journal › Debate/Note/Editorial
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Mark
Formation of the axial heterojunction in GaSb/InAs(Sb) nanowires with high crystal quality
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- Contribution to journal › Article
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Mark
An Analog (7,5) Convolutional Decoder in 65 nm CMOS for Low Power Wireless Applications
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- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low Complexity Soft-Output Signal Detector for Spatial-Multiplexing MIMO System
2011) 22nd Annual IEEE symposium on Personal Indoor Mobile Radio Communications (PIMRC 2011) p.1718-1722(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Complexity analysis of IOTA filter architectures in Faster-than-Nyquist multicarrier systems
2011) 29th Norchip conference, 2011(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding