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- 2019
-
Mark
Dimension Engineering of High-Quality InAs Nanostructures on a Wafer Scale
- Contribution to journal › Article
-
Mark
Charge transport in III-V narrow bandgap semiconductor nanowires
(2019)
- Thesis › Doctoral thesis (compilation)
-
Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
- Contribution to journal › Article
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
- Contribution to journal › Article
-
Mark
Vertical nanowire TFETs with channel diameter down to 10 nm and point S MIN of 35 mV/decade
- Contribution to journal › Article
-
Mark
Nanowire morphology and particle phase control by tuning the in concentration of the foreign metal nanoparticle
- Contribution to journal › Article
- 2017
-
Mark
Properties of III-V nanowires : MOSFETs and TunnelFETs
(2017) 2017 Joint International EUROSOl Workshop and International Conference on Ultimate Integration on Silicon-ULIS, EUROSOI-ULIS 2017 p.99-100
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Vertical III-V Nanowire Tunnel Field-Effect Transistor
(2017)
- Thesis › Doctoral thesis (compilation)
-
Mark
Phase diagrams for understanding gold-seeded growth of GaAs and InAs nanowires
- Contribution to journal › Article
-
Mark
Individual Defects in InAs/InGaAsSb/GaSb Nanowire Tunnel Field-Effect Transistors Operating below 60 mV/decade
(2017) In Nano Letters
- Contribution to journal › Letter
