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- 2020
-
Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2017
-
Mark
Vertical heterojunction InAs/InGaAs nanowire MOSFETs on Si with Ion = 330 μa/μm at Ioff = 100 nA/μm and VD = 0.5 v
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Vertical InAs/GaAsSb/GaSb tunneling field-effect transistor on Si with S = 48 mV/decade and Ion = 10 μA/μm for Ioff = 1 nA/μm at VDS = 0.3 V
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
Electrical Characterization and Modeling of Gate-Last Vertical InAs Nanowire MOSFETs on Si
(
- Contribution to journal › Letter
-
Mark
Self-aligned, gate-last process for vertical InAs nanowire MOSFETs on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scaling of Vertical InAs–GaSb Nanowire Tunneling Field-Effect Transistors on Si
(
- Contribution to journal › Letter
- 2014
-
Mark
Design of Radial Nanowire Tunnel Field-Effect Transistors
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Extrinsic and Intrinsic Performance of Vertical InAs Nanowire MOSFETs on Si Substrates
(
- Contribution to journal › Article
-
Mark
GaSb nanowire pFETs for III-V CMOS
2013) 71th Annual Device Research Conference (DRC) In IEEE Device Research Conference. Proceedings p.13-14(
- Contribution to journal › Published meeting abstract
- 2012
-
Mark
InAs Nanowires for High Frequency Electronics
2012) GigaHertz Symposium 2012(
- Contribution to conference › Abstract