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- 2023
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Mark
Low-Power, Self-Aligned Vertical InGaAsSb NW PMOS With S < 100 mV/dec
(
- Contribution to journal › Article
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Mark
Vertical III-V Nanowire Transistors for Low-Power Electronics
2023)(
- Thesis › Doctoral thesis (compilation)
- 2020
-
Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
-
Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article