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- 2020
-
Mark
A 10-bit Split-Capacitor SAR ADC with DAC Imbalance Estimation and Calibration
2020) 2020 IEEE International Symposium on Circuits and Systems (ISCAS)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Design Method to Minimize the Impact of Bit Conversion Errors in SAR ADCs
2020) 2020 Nordic Circuits and Systems Conference (NORCAS): NORCHIP & International Symposium on System-on-Chip (SoC)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2019
-
Mark
A 5 GHz CT ^Delta;Σ ADC with 250 MHz Signal Bandwidth in 28 nm-FDSOI CMOS
2019) 5th IEEE Nordic Circuits and Systems Conference, NORCAS 2019: NORCHIP and International Symposium of System-on-Chip, SoC 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
- 2017
-
Mark
Design considerations for 5G mm-wave receivers
2017) 2017 Fifth International Workshop on Cloud Technologies and Energy Efficiency in Mobile Communication Networks (CLEEN)(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 12b, 1 GSps TI pipelined-SAR converter with 65 dB SFDR through buffer linearization and gain mismatch correction in 28nm FD-SOI
2017) 43rd IEEE European Solid State Circuits Conference, ESSCIRC 2017(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2016
-
Mark
A 65 nm CMOS Wideband Radio Receiver with ΔΣ-Based A/D-Converting Channel-Select Filters
(
- Contribution to journal › Article
- 2015
-
Mark
A low-power 2nd-order CT delta-sigma modulator with an asynchronous SAR quantizer
(
- Contribution to journal › Article
-
Mark
A 0.6-3.0 GHz 65 nm CMOS Radio Receiver with DS-based A/D-Converting Channel-Select Filters
2015) IEEE European Solid State Circuits Conference, ESSCIRC 2015(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2014
-
Mark
Radio Electronics
2014)(
- Book/Report › Book
-
Mark
A low-power 2nd-order CT delta-sigma modulator with a single operational amplifier
(
- Contribution to journal › Article
-
Mark
An 11mW Continuous Time Delta-Sigma Modulator with 20 MHz Bandwidth in 65nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Filtering Delta Sigma ADC for LTE and Beyond
(
- Contribution to journal › Article
- 2013
-
Mark
Theory and Design of a CT Delta Sigma Modulator with Low Sensitivity to Loop-Delay Variations
(
- Contribution to journal › Article
-
Mark
A 9MHz Filtering ADC with Additional 2nd-Order Delta-Sigma Modulator Noise Suppression
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Design of a Configurable Analog Receiver Front-End Supporting LTE Carrier Aggregation
2013) IEEE Vehicular Technology Conference (VTC 2013)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS
(
- Contribution to journal › Article
-
Mark
A Receiver for LTE Rel-11 and Beyond Supporting Non-Contiguous Carrier Aggregation
2013) International Solid-State Circuits Conference, ISSCC, 2013(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2012
-
Mark
A Continuous Time Delta-Sigma Modulator with Reduced Clock Jitter Sensitivity through DSCR Feedback
2012) In Analog Integrated Circuits and Signal Processing(
- Contribution to journal › Article
-
Mark
A 7.5 mW 9 MHz CT Delta-Sigma Modulator in 65 nm CMOS with 69 dB SNDR and Reduced Sensitivity to Loop Delay Variations
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Harmonic Rejection Mixer at ADC Input for Complex IF Dual Carrier Receiver Architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A 4.75-34.75 MHz Digitally Tunable Active-RC LPF for > 60 dB RX IRR in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Complex IF Harmonic Rejection Mixer for Non-Contiguous Dual Carrier Reception in 65 nm CMOS
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2011
-
Mark
A continuous time delta sigma modulator with reduced clock jitter through DSCR feedback
2011) 29th Norchip conference, 2011(
- Contribution to conference › Paper, not in proceeding
-
Mark
A 9-band WCDMA/EDGE transceiver supporting HSPA evolution
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2010
-
Mark
Impact of MOS threshold-voltage mismatch in current-steering DACs for CT delta-sigma modulators
(
- Contribution to conference › Paper, not in proceeding
- 2009
-
Mark
DT Modeling of Clock Phase Noise Effects in LP CT Delta-Sigma ADCs with RZ Feedback
(
- Contribution to journal › Article
-
Mark
Design and measurement of a CT delta-sigma ADC with switched-capacitor switched-resistor feedback
(
- Contribution to journal › Article
- 2007
-
Mark
A 312-MHz CT Delta Sigma modulator using a SC feedback DAC with reduced peak current
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2005
-
Mark
Spectrum emission considerations for baseband-modeled CALLUM architectures
(
- Contribution to journal › Article
- 2004
-
Mark
Fast and accurate ACLR estimation method
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Implementation of the signal component generator of a CALLUM 2 transmitter architecture in CMOS technology
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2002
-
Mark
Effects of anti-aliasing filters in feedback path of adaptive predistortion
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A voltage-translinear based CMOS signal component separator chip for linear LINC transmitters
(
- Contribution to journal › Article
-
Mark
Bandwidth considerations for a CALLUM transmitter architecture
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2000
-
Mark
A chip for linearization of RF power amplifiers using predistortion based on a bit-parallel complex multiplier
(
- Contribution to journal › Article
- 1999
-
Mark
A chip for linearization of RF power amplifiers using digital predistortion with a bit-parallel complex multiplier
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 1997
-
Mark
Chip for wideband digital predistortion RF power amplifier linearisation
(
- Contribution to journal › Article