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- 2015
-
Mark
Abort-on-Fail Test Scheduling for Modular SOCs without and with Preemption
(
- Contribution to journal › Article
- 2014
-
Mark
Test Planning and Test Access Mechanism Design for Stacked Chips using ILP
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning and Test Access Mechanism Design for 3D SICs
2014) Swedish System on Chip Conference (SSoCC), 2014(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2013
-
Mark
Test Planning for 3D SICs using ILP
2013) Swedish System-On-Chip Conference (SSoCC), 2013(
- Contribution to conference › Paper, not in proceeding
- 2012
-
Mark
Test Planning for Core-based 3D Stacked ICs with Through-Silicon Vias
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Planning for Core-based 3D Stacked ICs under Power Constraints
2012) IEEE International Workshop on Realiability Aware System Design and Test (RASDAT 2012)(
- Contribution to conference › Paper, not in proceeding
- 2011
-
Mark
Test Scheduling in an IEEE P1687 Environment with Resource and Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Scheduling Tests for 3D Stacked Chips under Power Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for 3D Stacked ICs under Power Constraints
2011) 2nd IEEE International Workshop on Reliability Aware System Design and Test (RASDAT)(
- Contribution to conference › Paper, not in proceeding
-
Mark
Test Cost Modeling for 3D Stacked Chips with Through-Silicon Vias
2011) Swedish System-on-Chip Conference, SSoCC 2011(
- Contribution to conference › Paper, not in proceeding
- 2010
-
Mark
Scheduling Tests for Stacked 3D Chips under Power Constraints
2010) Swedish SoC Conference 2010(
- Contribution to conference › Paper, not in proceeding
- 2008
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Architecture Design and Scheduling
2008) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 27(5). p.973-977(
- Contribution to journal › Article
-
Mark
A reconfigurable power conscious core wrapper and its application to system-on-chip test scheduling
(
- Contribution to journal › Article
-
Mark
Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2007
-
Mark
Optimized Integration of Test Compression and Sharing for SOC Testing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Heuristic for Concurrent SOC Test Scheduling with Compression and Sharing
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2006
-
Mark
Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Power-Aware Test Planning in the Early System-On-Chip Design Exploration Process
(
- Contribution to journal › Article
-
Mark
System-on-chip test scheduling with reconfigurable core wrappers
(
- Contribution to journal › Article
- 2005
-
Mark
Abort-on-Fail Based Test Scheduling
(
- Contribution to journal › Article
-
Mark
SOC Test Scheduling with Test Set Sharing and Broadcasting
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Scheduling for Modular SOCs in an Abort-on-Fail Environment
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Combined Test Data Selection and Scheduling for Test Quality Optimization under ATE Memory Depth Constraint
2005) IFIP WG 10.5 Conference on Very Large Scale Integration System-on-Chip {IFIP VLSI-SOC 2005} p.429-434(
- Contribution to conference › Paper, not in proceeding
- 2004
-
Mark
Defect-Aware SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Integrating Core Selection in the SOC Test Solution Design-Flow
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Efficient test solutions for core-based designs
2004) In IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems 23(5). p.758-775(
- Contribution to journal › Article
-
Mark
Preemptive system-on-chip test scheduling
(
- Contribution to journal › Article
- 2003
-
Mark
Buffer and Controller Minimization for Time-Constrained Testing of System-On-Chip
2003) 18th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems DFT03 p.385-392(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
SOC Test Time Minimization Under Multiple Constraints
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Test Resource Partitioning and Optimization for SOC Designs
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
Optimal System-on-Chip Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
A Reconfigurable Power-conscious Core Wrapper and its Application to SOC Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Scheduling based on Defect Probability
2003)(
- Other contribution › Miscellaneous
- 2002
-
Mark
Integrated Test Scheduling, Test Parallelization and TAM Design
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
An Integrated Framework for the Design and Optimization of SOC Test Solutions
(
- Contribution to journal › Article
- 2001
-
Mark
Test Scheduling and Scan-Chain Division Under Power Constraint
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2000
-
Mark
A Technique for Test Infrastructure Design and Test Scheduling
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
-
Mark
System-on-Chip Test Bus Design and Test Scheduling
2000) International Test Synthesis Workshop,2000(
- Contribution to conference › Paper, not in proceeding