Skip to main content

Lund University Publications

LUND UNIVERSITY LIBRARIES

Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications

Jönsson, Adam LU (2021)
Abstract
This thesis focuses mainly on the co-integration of vertical nanowire
n-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), where
MOVPE grown vertical InAs-GaSb heterostructure nanowires are
used for realizing monolithically integrated and co-processed all-III-V CMOS.
Utilizing a bottom-up approach based on MOVPE grown nanowires enables
design flexibilities, such as in-situ doping and heterostructure formation,
which serves to reduce the amount of mask steps during fabrication. By refining
the fabrication techniques, using a self-aligned gate-last process, scaled
10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100
μA/μm, considering Ioff at 100 nA/μm... (More)
This thesis focuses mainly on the co-integration of vertical nanowire
n-type InAs and p-type GaSb MOSFETs on Si (Paper I & II), where
MOVPE grown vertical InAs-GaSb heterostructure nanowires are
used for realizing monolithically integrated and co-processed all-III-V CMOS.
Utilizing a bottom-up approach based on MOVPE grown nanowires enables
design flexibilities, such as in-situ doping and heterostructure formation,
which serves to reduce the amount of mask steps during fabrication. By refining
the fabrication techniques, using a self-aligned gate-last process, scaled
10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100
μA/μm, considering Ioff at 100 nA/μm (VDD = 0.5 V). This is enabled
by greatly improved p-type MOSFET performance reaching a maximum
transconductance of 260 μA/μm at VDS = 0.5 V. Lowered power dissipation
for CMOS circuits requires good threshold voltage VT matching of the n- and
p-type device, which is also demonstrated for basic inverter circuits. The
various effects contributing to VT-shifts are also studied in detail focusing on
the InAs channel devices (with highest transconductance of 2.6 mA/μm), by
using Electron Holography and a novel gate position variation method (Paper
V).
The advancements in all-III-V CMOS integration spawned individual studies
into the strengths of the n- and p-type III-V devices, respectively. Traditionally
materials such as InAs and InGaAs provide excellent electron
transport properties, therefore they are frequently used in devices for high
frequency RF applications. In contrast, the III-V p-type alternatives have been
lacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFET
channel, was designed and enabled by new manufacturing techniques, which
allowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs
(Paper III). The new fabrication method allowed for integration of devices
with symmetrical contacts as compared to previous work which relied on a
tunnel-contact at the source-side. By modelling based on measured data fieldeffect
hole mobility of 70 cm2/Vs was calculated, well in line with previously
reported studies on GaSb nanowires. The oxidation properties of the GaSb
gate-stack was further characterized by XPS, where high intensities of xrays
are achieved using a synchrotron source allowed for characterization of
nanowires (Paper VI). Here, in-situ H2-plasma treatment, in parallel with XPS
measurements, enabled a study of the time-dependence during full removal
of GaSb native oxides.
The last focus of the thesis was building on the existing strengths of vertical
heterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,
these devices demonstrate high-current densities (gm >3 mS/μm) and excellent
modulation properties (off-state current down to 1 nA/μm). However,
minimizing the parasitic capacitances, due to various overlaps originating
from a low access-resistance design, has proven difficult. Therefore, new
methods for spacers in both the vertical and planar directions was developed
and studied in detail. The new fabrication methods including sidewall spacers
achieved gate-drain capacitance CGD levels close to 0.2 fF/μm, which is
the established limit by optimized high-speed devices. The vertical spacer
technology, using SiO2 on the nanowire sidewalls, is further improved in
this thesis which enables new co-integration schemes for memory arrays.
Namely, the refined sidewall spacer method is used to realize selective recess
etching of the channel and reduced capacitance for large array memory
selector devices (InAs channel) vertically integrated with Resistive Random
Access Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-
memristor (1T1R) demonstrator cell shows excellent endurance and retention
for the RRAM by maintaining constant ratio of the high and low resistive state
(HRS/LRS) after 106 switching cycles.
(Less)
Please use this url to cite or link to this publication:
author
supervisor
opponent
  • Prof. Voon - Yew Thean, Aaron, University of Singapore, Singapore.
organization
publishing date
type
Thesis
publication status
published
subject
keywords
Nanowire, MOSFET, CMOS, RRAM, III-V, InAs, GaSb, InGaAs, Heterostructure, vertical, nanowire (NW), MOSFET, III-V materials, RRAM, RF, CMOS, InAs, GaSb, InGaAs, heterostructure, Vertical nanowire
publisher
Electrical and Information Technology, Lund University
defense location
Lecture hall E:B, building E, Ole Römers väg 3, Faculty of Engineering LTH, Lund University, Lund. Zoom: https://lu-se.zoom.us/j/62109748570?pwd=YUVBUGZkZlZPdGlUeWJwbjhtY3JVUT09
defense date
2021-09-17 09:15:00
ISBN
978-91-7895-975-4
978-91-7895-976-1
language
English
LU publication?
yes
id
8519af5a-52e1-4b09-875c-eae775eb45cb
date added to LUP
2021-08-26 16:20:37
date last changed
2022-04-07 10:12:41
@phdthesis{8519af5a-52e1-4b09-875c-eae775eb45cb,
  abstract     = {{This thesis focuses mainly on the co-integration of vertical nanowire<br/>n-type InAs and p-type GaSb MOSFETs on Si (Paper I &amp; II), where<br/>MOVPE grown vertical InAs-GaSb heterostructure nanowires are<br/>used for realizing monolithically integrated and co-processed all-III-V CMOS.<br/>Utilizing a bottom-up approach based on MOVPE grown nanowires enables<br/>design flexibilities, such as in-situ doping and heterostructure formation,<br/>which serves to reduce the amount of mask steps during fabrication. By refining<br/>the fabrication techniques, using a self-aligned gate-last process, scaled<br/>10-20 nm diameters are achieved for balanced drive currents at Ion ∼ 100<br/>μA/μm, considering I<sub>off</sub> at 100 nA/μm (V<sub>DD</sub> = 0.5 V). This is enabled<br/>by greatly improved p-type MOSFET performance reaching a maximum<br/>transconductance of 260 μA/μm at V<sub>DS</sub> = 0.5 V. Lowered power dissipation<br/>for CMOS circuits requires good threshold voltage V<sub>T</sub> matching of the n- and<br/>p-type device, which is also demonstrated for basic inverter circuits. The<br/>various effects contributing to V<sub>T</sub>-shifts are also studied in detail focusing on<br/>the InAs channel devices (with highest transconductance of 2.6 mA/μm), by<br/>using Electron Holography and a novel gate position variation method (Paper<br/>V).<br/>The advancements in all-III-V CMOS integration spawned individual studies<br/>into the strengths of the n- and p-type III-V devices, respectively. Traditionally<br/>materials such as InAs and InGaAs provide excellent electron<br/>transport properties, therefore they are frequently used in devices for high<br/>frequency RF applications. In contrast, the III-V p-type alternatives have been<br/>lacking performance mostly due to the difficult oxidation properties of Sb-based materials. Therefore, a study of the GaSb properties, in a MOSFET<br/>channel, was designed and enabled by new manufacturing techniques, which<br/>allowed gate-length scaling from 40 to 140 nm for p-type Sb-based MOSFETs<br/>(Paper III). The new fabrication method allowed for integration of devices<br/>with symmetrical contacts as compared to previous work which relied on a<br/>tunnel-contact at the source-side. By modelling based on measured data fieldeffect<br/>hole mobility of 70 cm<sup>2</sup>/Vs was calculated, well in line with previously<br/>reported studies on GaSb nanowires. The oxidation properties of the GaSb<br/>gate-stack was further characterized by XPS, where high intensities of xrays<br/>are achieved using a synchrotron source allowed for characterization of<br/>nanowires (Paper VI). Here, in-situ H<sup>2</sup>-plasma treatment, in parallel with XPS<br/>measurements, enabled a study of the time-dependence during full removal<br/>of GaSb native oxides.<br/>The last focus of the thesis was building on the existing strengths of vertical<br/>heterostructure III-V n-type (InAs-InGaAs graded channel) devices. Typically,<br/>these devices demonstrate high-current densities (g<sub>m</sub> &gt;3 mS/μm) and excellent<br/>modulation properties (off-state current down to 1 nA/μm). However,<br/>minimizing the parasitic capacitances, due to various overlaps originating<br/>from a low access-resistance design, has proven difficult. Therefore, new<br/>methods for spacers in both the vertical and planar directions was developed<br/>and studied in detail. The new fabrication methods including sidewall spacers<br/>achieved gate-drain capacitance C<sub>GD</sub> levels close to 0.2 fF/μm, which is<br/>the established limit by optimized high-speed devices. The vertical spacer<br/>technology, using SiO<sub>2</sub> on the nanowire sidewalls, is further improved in<br/>this thesis which enables new co-integration schemes for memory arrays.<br/>Namely, the refined sidewall spacer method is used to realize selective recess<br/>etching of the channel and reduced capacitance for large array memory<br/>selector devices (InAs channel) vertically integrated with Resistive Random<br/>Access Memory (RRAM) memristors. (Paper IV) The fabricated 1-transistor-1-<br/>memristor (1T1R) demonstrator cell shows excellent endurance and retention<br/>for the RRAM by maintaining constant ratio of the high and low resistive state<br/>(HRS/LRS) after 10<sup>6</sup> switching cycles.<br/>}},
  author       = {{Jönsson, Adam}},
  isbn         = {{978-91-7895-975-4}},
  keywords     = {{Nanowire; MOSFET; CMOS; RRAM; III-V; InAs; GaSb; InGaAs; Heterostructure; vertical; nanowire (NW); MOSFET; III-V materials; RRAM; RF; CMOS; InAs; GaSb; InGaAs; heterostructure; Vertical nanowire}},
  language     = {{eng}},
  month        = {{08}},
  publisher    = {{Electrical and Information Technology, Lund University}},
  school       = {{Lund University}},
  title        = {{Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications}},
  url          = {{https://lup.lub.lu.se/search/files/111643335/DoctoralThesis_copyrightAdamJonsson.pdf}},
  year         = {{2021}},
}