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- 2021
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Mark
Doping Profiles in Ultrathin Vertical VLS-Grown InAs Nanowire MOSFETs with High Performance
(
- Contribution to journal › Article
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Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
(
- Contribution to journal › Article
-
Mark
Vertical Heterostructure III-V MOSFETs for CMOS, RF and Memory Applications
2021)(
- Thesis › Doctoral thesis (compilation)
- 2020
-
Mark
Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
- 2019
-
Mark
Balanced Drive Currents in 10–20 nm Diameter Nanowire All-III-V CMOS on Si
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
- 2018
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
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Mark
CMOS Integration Based on All-III-V Materials
2018) Swedish Microwave Days 2018(
- Contribution to conference › Abstract
-
Mark
Vertical, High-Performance 12 nm diameter InAs Nanowire MOSFETs on Si using an all III-V CMOS process
2018) Compound Semiconductor Week 2018(
- Contribution to conference › Abstract