Saketh Ram Mamidala (Former)
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- 2023
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Mark
Vertical III-V Nanowires For In-Memory Computing
2023)(
- Thesis › Doctoral thesis (compilation)
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Mark
Effects of Interface Oxidation on Noise Properties and Performance in III–V Vertical Nanowire Memristors
(
- Contribution to journal › Article
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Mark
Self-Heating in Gate-All-Around Vertical III-V InAs/InGaAs MOSFETs
(
- Contribution to journal › Article
- 2022
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Mark
Performance, Analysis, and Modeling of III-V Vertical Nanowire MOSFETs on Si at Higher Voltages
(
- Contribution to journal › Article
-
Mark
The Effect of Deposition Conditions on Heterointerface-Driven Band Alignment and Resistive Switching Properties
(
- Contribution to journal › Article
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Mark
A 4F2 Vertical Gate-all-around Nanowire Compute-in-memory Device Integrated in (1T1R) Cross-Point Arrays on Silicon
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low-Frequency Noise in Vertical InAs/InGaAs Gate-All-Around MOSFETs at 15 K for Cryogenic Applications
(
- Contribution to journal › Article
- 2021
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Mark
Ultra-Scaled AlOx Diffusion Barriers for Multibit HfOx RRAM Operation
(
- Contribution to journal › Article
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Mark
Tuning oxygen vacancies and resistive switching properties in ultra-thin HfO2 RRAM via TiN bottom electrode and interface engineering
(
- Contribution to journal › Article
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Mark
High-density logic-in-memory devices using vertical indium arsenide nanowires on silicon
(
- Contribution to journal › Article