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- 2020
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Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article
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Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
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Mark
A method for estimating defects in ferroelectric thin film MOSCAPs
(
- Contribution to journal › Article
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Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Tuning of Source Material for InAs/InGaAsSb/GaSb Application-Specific Vertical Nanowire Tunnel FETs
(
- Contribution to journal › Article
- 2019
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Mark
Electrical Properties of Vertical InAs/InGaAs Heterostructure MOSFETs
(
- Contribution to journal › Article
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Mark
Vertical Gate-All-Around Nanowire GaSb-InAs Core-Shell n-Type Tunnel FETs
(
- Contribution to journal › Article
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Mark
An Experimental Study of Heterostructure Tunnel FET Nanowire Arrays : Digital and Analog Figures of Merit from 300K to 10K
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Low-Temperature Front-Side BEOL Technology with Circuit Level Multiline Thru-Reflect-Line Kit for III-V MOSFETs on Silicon
2019) 92nd ARFTG Microwave Measurement Conference, ARFTG 2019(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
Trap-aware compact modeling and power-performance assessment of III-V tunnel FET
2019) 2018 IEEE SOI-3D-Subthreshold Microelectronics Technology Unified Conference, S3S 2018(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding