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- 2020
-
Mark
Low-Power Resistive Memory Integrated on III-V Vertical Nanowire MOSFETs on Silicon
(
- Contribution to journal › Article
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Mark
Vertical InAs/InGaAsSb/GaSb Nanowire Tunnel FETs on Si with Drain Field-Plate and EOT = 1 nm Achieving Smin= 32 mV/dec and gm/ID= 100 V-1
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding
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Mark
III-V nanowire MOSFETs with novel self-limiting Λ-ridge spacers for RF applications
(
- Contribution to journal › Article
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Mark
Gate-Length Dependence of Vertical GaSb Nanowire p-MOSFETs on Si
(
- Contribution to journal › Article
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Mark
Nanowire Tunnel FET with Simultaneously Reduced Subthermionic Subthreshold Swing and Off-Current due to Negative Capacitance and Voltage Pinning Effects
(
- Contribution to journal › Article
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Mark
Mobility of near surface MOVPE grown InGaAs/InP quantum wells
(
- Contribution to journal › Article
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Mark
Strain mapping inside an individual processed vertical nanowire transistor using scanning X-ray nanodiffraction
(
- Contribution to journal › Article
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Mark
Feature size control using surface reconstruction temperature in block copolymer lithography for InAs nanowire growth
(
- Contribution to journal › Article
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Mark
Compressively-strained GaSb nanowires with core-shell heterostructures
(
- Contribution to journal › Article
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Mark
High-Performance Vertical III-V Nanowire MOSFETs on Si with gm> 3 mS/μm
(
- Contribution to journal › Article