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- 2019
-
Mark
A 10-mW mm-Wave Phase-Locked Loop With Improved Lock Time in 28-nm FD-SOI CMOS
(
- Contribution to journal › Article
-
Mark
Integrated Transmitters for Cellular User Equipment–Wideband CMOS Power Amplifiers and Antenna Impedance Tuners
2019)(
- Thesis › Doctoral thesis (compilation)
- 2018
-
Mark
A 28-nm FD-SOI 115-fs Jitter PLL-Based LO System for 24-30-GHz Sliding-IF 5G Transceivers
(
- Contribution to journal › Article
-
Mark
A Self-aligned Gate-last Process applied to All-III-V CMOS on Si
(
- Contribution to journal › Article
- 2017
-
Mark
Digital Phase Locked Loops for Radio Frequency Synthesis
2017)(
- Thesis › Doctoral thesis (monograph)
-
Mark
Ultra-wideband transmitter design based on a new transmitted reference pulse cluster
(
- Contribution to journal › Article
- 2016
-
Mark
A 2.8-to-5.8 GHz harmonic VCO based on an 8-shaped inductor in a 28 nm UTBB FD-SOI CMOS process
(
- Contribution to journal › Article
-
Mark
Ultra-low Voltage Embedded Memories – Design Aspects and a Biomedical Use-case
2016)(
- Thesis › Doctoral thesis (compilation)
- 2015
-
Mark
III-V Nanowire Complementary Metal-Oxide Semiconductor Transistors Monolithically Integrated on Si
(
- Contribution to journal › Article
-
Mark
A 2.8-to-5.8 GHz harmonic VCO in a 28 nm UTBB FD-SOI CMOS process
(
- Chapter in Book/Report/Conference proceeding › Paper in conference proceeding